1. Field of the Invention
The present invention relates to a semiconductor device having MOSFETs and a method for manufacturing the semiconductor device.
2. Related Art
The advent of ultrahigh-speed and high-functionality semiconductor devices had spurred rapid evolution of an information-oriented and knowledge-intensive society into a global web of high-speed communication networks, as exemplified by the ubiquitous presence of radiofrequency cellular or “mobile” phones in daily lives. Naturally, the world-wide spread of such social transformation, as well as an insatiable quest for more efficient and convenient life-styles, demands yet higher-speed operation of ever-shrinking semiconductor devices being integrated on a much larger scale, to realize a system-on-chip versatile architecture which provides almost every conceivable functionality.
As a matter of course, to meet the above demand, the physical dimensions of principal components of a large scale integration (LSI) circuit, i.e., metal insulator semiconductor field effect transistors (MISFET's), or more specifically, metal oxide semiconductor field effect transistors (MOSFET's), have to be reduced accordingly.
Unfortunately, however, further miniaturizing the MOSFET dimensions while speeding-up its operation becomes increasingly a difficult task to achieve. In fact, as explained below, various technical difficulties arise from this attempt.
One of such difficulties arises from sharp decrease of threshold voltage with the downscaling or shrinkage of the channel length of the MOSFET (i.e., reduction of the physical length of the gate electrode), widely known as the short channel effect. When the threshold voltage comes to depend on the physical gate length, even a slight process variation during the gate electrode formation results in uncontrollable deviation in the threshold voltage. Of course, a MOSFET with an unintended threshold voltage, when it is very different from the designed value, gives rise to erratic device operations which is incompatible with the original intention of the device and may well totally impair the proper functionality of the entire circuit.
Obviously, in order to obtain a large number of coherent and identical MOSFETs, the short-channel-effect-induced strong dependence of the threshold voltage on the physical gate length is extremely detrimental. The resultant intolerance of even a minute process deviation during the device fabrication makes it very difficult to manufacture efficiently an electric circuit composed of a great number of uniform and densely-packed elements, such as a dynamic random access memory (DRAM).
In view of its physical mechanism, this short channel effect is a result of distortion of an electric potential near the central portion of the channel region induced by electric fields at source/drain (S/D) electrodes. As the channel length decreases, the influence of S/D electric fields comes to reach the central portion of the channel, allowing premature channel currents to flow between S/D electrodes even when the gate voltage is below the intended value (i.e., reducing the threshold voltage).
As widely recognized, by making the p-n junctions that forms S/D regions (i.e., S/D p-n junctions) shallower, the short channel effect can be avoided. However, simply making the S/D p-n junctions very shallow inevitably results in unacceptable increase in the electrical resistances of the S/D electrodes. The resistance increase impedes high-speed transmission of electrical signals through the MOSFET, thereby, totally dashing the original intention of miniaturizing the MOSFET dimensions to speed-up its operation.
One of the best ways of reducing the S/D electrode resistance is silicidation (i.e., compound formation between silicon and metal substance) of upper parts of S/D p-n junctions. The metal species that could be used for this purpose includes cobalt (Co), titanium (Ti) and nickel (Ni). However, of these metals, Ni is the primary choice for the silicidation of fine structures employed by today's ULSI technology. This is because it is free from adverse line-width effects (i.e., resistivity increase of silicide layers when they are formed on narrow lines).
In addition, the silicidation reaction between Si and Ni can be completed at a temperature as low as 450° C., which is much lower than the CoSi2 formation temperature (i.e., 800° C.). Moreover, this low temperature thermal treatment produces a layer of NiSi, which has a very low resistivity. Applying thermal processing at a higher temperature of about 750° C. causes an unfavorable phase transition of the NiSi layer into a layer of NiSi2, that has a higher electrical resistivity than that of NiSi. Thus, naturally, it is this NiSi layer of low resistance that is typically used for ULSI devices.
Unfortunately, however, NiSi is not a problem-free option. In fact, its thermal stability is the greatest concern of the NiSi technology. In general, after having formed the low-resistance NiSi layer, it is indispensable to perform thermal processing at 500° C. for about 90 minutes, for example, in order to establish good electrical contact between the NiSi layer and a metal substance formed thereon. However, even this moderate thermal processing (i.e., at 500° C. for 90 min) is found to trigger a substantial burst of Ni atoms from the NiSi layer deep into the Si substrate, even reaching a depth of about 140 nm, though it is done at a temperature well below the phase transition temperature (as disclosed by M. Tsuchiaki, Jpn. J. Appl. Phys., Vol. 43, p. 5166 (2004), for example).
Of course, the Ni atoms that infiltrated deeply into the Si substrate form gap states in the forbidden band of Si, thereby assisting or promoting leakage generation. Since this Ni burst into the Si substrate is an intrinsic characteristic of NiSi, it proceeds unavoidably whenever NiSi and Si are in physical contact at an elevated temperature. Obviously, once such gap states are formed at the S/D junctions, substantial leakage currents flow through the junctions into the Si substrate, and eventually, an intended functionality of the device will be completely lost (e.g., loss of data memorized in DRAM cells).
In order to solve the aforementioned problems, an elevated source drain method has been commonly utilized. In this method, semiconductor layers are selectively formed (for example, silicon is grown) on surface portions of a semiconductor substrate where source and drain electrodes are to be formed. Because the surfaces of this additionally formed semiconductor layers are higher than the original semiconductor surface (i.e., the surface where a channel is to be formed), pn junction depths of the source and drain regions are shallow relative to the original semiconductor surface, but deep relative to the newly formed surfaces, securing the enough depth of the electrode while suppressing the short channel effects. Such a selective silicon growth can be achieved by using an epitaxial growth method.
Unfortunately, however, the thickness of the selectively grown silicon layer tends to decrease when it nears the gate electrode. Accordingly, the shortest distance between the additional surface (where the metal is to be deposited) and the junction depth is predetermined at this portion adjacent to the gate electrode. Thus, no matter how thick the selectively grown silicon layer is made at the other portions, its ability to block the leakage generation is not enhanced.
As described above, shrinkage of the MOSFET's dimensions requires commensurate shallowing of the source and drain junctions. At the same time, to secure high speed operation, silicidation of the source and drain regions is necessary.
However, for silicidation of shallow junctions (e.g., source/drain extension regions next to the gate electrode), the high-speed diffusion of metal atoms from the silicide causes substantial junction leakage current. The leakage is so devastating that metal compound formation on the source/drain extension regions is practically prohibited.
Without silicidation, however, the electric resistance around the source/drain extension regions becomes very high, causing a large potential drop at these portions. Since voltages applied to the source/drain electrodes are largely wasted, they cannot induce sufficient channel currents. Obviously, a MOSFET with high-speed operation cannot be obtained without silicidation of the source/drain extension regions.
Therefore, to prevent generation of junction leakage current due to silicidation of the shallow source/drain extension regions, it is necessary to develop a new method for suppressing infiltration of metallic atoms from the silicide layer into the substrate in the region adjacent to the gate electrode.